1. Field of the Invention
The present invention relates to an active matrix system organic electric luminescence (EL) display device, and to a method of driving thereof.
2. Description of the Related Art
Current controlling type organic light-emitting diodes (OLEDs) are used in active matrix system organic EL display devices. Accordingly, a selection transistor, a retention capacitor, and a driving transistor are required, which is different than in a liquid crystal display (LCD).
Conventionally, a thin film transistor (TFT) made of low-temperature polysilicon or amorphous silicon is used as the driving transistor, as disclosed in Japanese Patent Application Laid-Open (JP-A) No. 8-234683. A low-temperature polysilicon TFT may provide a high mobility and threshold voltage stability, but there are problems with the uniformity of the mobility. An amorphous silicon TFT may provide uniformity of the mobility, but there are problems with the mobility being low and fluctuations in the threshold voltage over time.
Low uniformity of the mobility and threshold voltage stability are expressed as unevenness of the displayed image. Accordingly, as disclosed in JP-A No. 2003-255856, in the case of using an amorphous silicon TFT, compensation circuits of a diode connection system are provided within the pixel circuits, and threshold voltage correction by the parasitic capacitances of the OLEDs is performed. However, when such compensation circuits are provided, the pixel circuits become complex, which may lead to an increase in costs due to a deterioration in yield, and a decrease in the aperture ratio.
Thus, as threshold voltage correction of a diode connection system, JP-A No. 2003-271095 proposes a method of reducing the number of transistors by correcting the threshold voltage by charging operation to the OLED parasitic capacitances.
FIG. 12 is a drawing showing the pixel circuit structure disclosed in JP-A No. 2003-271095.
The pixel circuit shown in FIG. 12 has a selection gate connecting switch 100, a retention capacitor 102, a driving transistor 104, a current controlling element (OLED) 106, a parasitic capacitance 108 and a reset switch 110. The selection gate connecting switch 100 is formed from a thin film transistor. The gate thereof is connected to a row scan signal line (hereinafter called Scan line) 112, and one of the drain and the source is connected to a column data signal line (hereinafter called Data line) 114, and the other of the drain and the source is connected to the gate of the driving transistor 104.
The retention capacitor 102 is connected between the gate and the source of the driving transistor 104. The driving transistor 104 is formed from a thin film transistor. The gate thereof is connected to one of the drain and the source of the selection gate connecting switch 100, and to one end of the retention capacitor 102. The drain of the driving transistor 104 is connected to power supply Vdd, and the source is connected to the anode of the OLED 106.
The anode of the OLED 106 is connected to the source of the driving transistor 104, and the cathode is grounded. The OLED 106 emits light at a luminance that corresponds to the magnitude of the current of the driving transistor 104. The parasitic capacitance 108 is a parasitic capacitance between the electrodes of the OLED 106.
The reset switch 110 is connected between, on the one hand, the source of the driving transistor 104, and, on the other hand, the OLED 106 and the parasitic capacitance 108, and is connected to one end of the retention capacitor 102. The reset switch 110 is connected to a row reset signal line (hereinafter called Res line) 116, and turns on and off in accordance with a Reset signal supplied from the Res line 116.
Operation of the pixel circuit shown in FIG. 12 will be described here with reference to FIG. 13 through FIG. 17. FIG. 13 is a drawing showing examples of voltage waveforms during the operation time periods of the circuit. Vs is the source voltage of the driving transistor 104, and Vgs is the voltage between the gate and source of the driving transistor 104.
Time periods T1 through T4 shown in FIG. 13 are time periods expressing one display period of the pixel circuit. The time period before T1 of FIG. 13 shows the previous display period. Accordingly, during this previous display period, the voltage value that is applied to the Data line 114, the source voltage Vs of the driving transistor 104, and the voltage Vgs between the gate and the source of the driving transistor 104 are voltages corresponding to the previous display period. Here, the voltage ranges thereof are shown by mesh shading, and without the values thereof being specified in particular.
FIG. 14 through FIG. 17 are drawings schematically showing the on/off states and the flow of current of the selection gate connecting switch 100 and the reset switch 110 during the respective operation time periods that will be described hereinafter.
In time period T1 shown in FIG. 13, resetting operation is performed. In this resetting time period T1, the selection gate connecting switch 100 is turned on as shown in FIG. 14 due to a Scan signal that is supplied to the Scan line 112 by an unillustrated Scan driver, and voltage VB that is supplied to the Data line 114 by an unillustrated Data driver is applied to the gate of the driving transistor 104. Given that the light-emitting threshold voltage of the OLED 106 is Vf0 and the threshold voltage of the driving transistor 104 is Vth, the voltage VB that satisfies the condition “Vth<VB<Vf0+Vth” is applied to the gate of the driving transistor 104.
Further, in this resetting time period T1, the reset switch 110 is turned on due to a Reset signal that is supplied to the Res line 116 simultaneously with the Scan signal, the retention capacitor 102 and the parasitic capacitance 108 are discharged, and the source voltage Vs of the driving transistor 104 becomes 0 V. The resetting operation time period T1 is set in advance as the time period needed in order for the source voltage Vs of the driving transistor 104 to become 0 V.
In the technique disclosed in exemplary embodiment 1 of JP-A No. 2003-271095, this resetting operation is realized by natural discharging of OLED leak current, without providing the reset switch 110.
In time period T2 shown in FIG. 13, a threshold voltage detecting operation is performed. When time period T1 ends and time period T2 is started, the Reset signal is set to the non-selection level, and, as shown in FIG. 15, the reset switch 110 is turned off.
At the time of the start of T2, the source voltage Vs of the driving transistor 104 is 0 V, and the gate voltage Vg is the voltage VB. Therefore, the voltage Vgs between the gate and the source is Vgs>Vth, and current Id corresponding to the voltage Vgs between the gate and the source flows to the driving transistor 104.
Due to this current Id, the parasitic capacitance 108 is charged, and the source voltage Vs rises. Because the gate voltage Vg is fixed to Vg=VB, as the source voltage Vs rises, the voltage Vgs between the gate and the source decreases and the current Id decreases. In this process, the voltage Vgs between the gate and the source of the driving transistor 36 gradually approaches the threshold voltage Vth.
Then, when the current Id has become sufficiently small, the rise in the source voltage Vs stops.
Here, the saturated region current formula of a thin film transistor (TFT) is expressed asId=μ*Cox*(W/L)*(Vgs−Vth)2 where μ is the mobility, Cox is the electrostatic capacity per unit surface area of the gate insulating film, W is the channel width and L is the channel length. Therefore, voltage Vcs that is written to the retention capacitor 102 at this time is Vcs=Vgs=Vth.
A condition in order to make current not flow to the OLED 106 so that that OLED 106 does not emit light is that the source voltage Vs satisfiesVs=VB−Vth<Vf0.Accordingly, as described above, the voltage VB will beVB<Vf0+Vth. 
In the time period of T3 shown in FIG. 13, programming operation is performed. Here, the operation of setting the current that is desired to flow to the driving transistor 104 in actuality (i.e., making the retention capacitor 102 hold the voltage for making the current flow) is called programming operation. At the start of the programming operation time period T3, as shown in FIG. 16, the Data signal voltage of the Data line 114 is stepped-up from VB to VB+Vod. Accordingly, the gate voltage Vg of the driving transistor 104 becomes VB+Vod.
Here, Vod is the overdrive voltage of the driving transistor 104, and isVod=Vgs−Vth. 
The source voltage Vs is the divided voltage of the retention capacitor 102 and the parasitic capacitance 108. Therefore, given that the capacity of the retention capacitor 102 is Cs and the capacity of the parasitic capacitance 108 is Cd, the source voltage Vs is expressed asVs=VB−Vth+Vod*Cs/(Cd+Cs).However, if the capacity Cd of the parasitic capacitance 108 is greater by far than the capacity Cs of the retention capacitor 102 (Cd>>Cs), the source voltage Vs will be substantially equal to “VB−Vth”. Therefore, the voltage Vgs between the gate and the source of the driving transistor 104 becomesVgs=Vg−Vs=(VB+Vod)−(VB−Vth)=Vth+Vod. Thus, voltage that is substantially obtained by adding the overdrive voltage Vod to the threshold voltage Vth detected in the threshold voltage detection time period T2, is set at the retention capacitor 102 that is positioned between the gate and the source of the driving transistor 104. The voltage that is set here is called the program voltage.
In the time period of T4 shown in FIG. 13, light-emitting operation is performed. In the time period of the light-emitting time period T4 of FIG. 13, a voltage value corresponding to the next display time period is applied to the Data line 114. Here, the voltage range thereof is shown by mesh shading without specifying the Data signal voltage in particular.
In the light-emitting time period T4, the Scan signal becomes the non-selection level, and, as shown in FIG. 17, the selection gate connecting switch 100 turns off. Further, the voltages at both ends of the retention capacitor 102 are held as is. Due to the current Id that flows to the driving transistor 104, the parasitic capacitance 108 of the OLED 106 is charged, and the source voltage Vs rises. Moreover, the voltage Vgs between the gate and the source of the driving transistor 104 holds the program voltage as is. Accordingly, before long, the source voltage Vs exceeds the light-emitting threshold voltage Vf0 of the OLED 106, and the OLED 106 emits light.
The selection gate connecting switch 100 must be turned off at the time after application of the aforementioned overdrive voltage Vod is completed and before the source voltage Vs starts to rise.
Further, JP-A No. 2007-310311 discloses a device that adds a mobility μ correcting function to the above-described technique disclosed in JP-A No. 2003-271095.
FIG. 18 is a drawing showing the pixel circuit structure disclosed in JP-A No. 2007-310311. In FIG. 18, structural elements to which the same numerals as in FIG. 12 are applied are the same structural elements as in FIG. 12.
The pixel circuit shown in FIG. 18 has the selection gate connecting switch 100, the retention capacitor 102, the driving transistor 104, the OLED 106 and the parasitic capacitance 108. The relationships of connection among these respective elements are the same as in FIG. 12. However, the reset switch 110 is not provided in the circuit of FIG. 18. Further, the drain of the driving transistor 104 is connected to a power supply line (hereinafter called Vddx line) 118 that is common to the row.
The operation of the pixel circuit shown in FIG. 18 will be described with reference to FIG. 19, with the main point being the function of correcting the mobility μ. FIG. 19 is a drawing showing examples of the voltage waveforms during the operation time periods of the circuit.
In time period T1 shown in FIG. 19, resetting operation is performed. In this resetting time period T1, the selection gate connecting switch 100 is turned on due to the Scan signal that is supplied to the Scan line 112 by the unillustrated Scan driver, and the voltage VB that is supplied to the Data line 114 by the unillustrated Data driver is applied to the gate of the driving transistor 104. In the same way as in FIG. 12, given that the light-emitting threshold voltage of the OLED 106 is Vf0 and the threshold voltage of the driving transistor 104 is Vth, the voltage VB that satisfies the condition “Vth<VB<Vf0+Vth” is applied to the gate of the driving transistor 104.
Here, power supply voltage Vddx that is supplied from the Vddx line 118 is set to “Vddx=VL<VB−Vth”. Namely, the power supply voltage Vddx is made to be less than VB. Due thereto, the driving transistor 104 turns on, and, at the driving transistor 104, current flows from the parasitic capacitance 108 side to the Vddx line 118 side. Accordingly, the parasitic capacitance 108 of the OLED 106 discharges to the Vddx line 118, and finally, the source voltage Vs of the driving transistor 104 becomes 0 V. In this way, discharging of the parasitic capacitance 108 is performed without providing the reset switch 110 in this structure.
In the time period of T2 shown in FIG. 19, threshold voltage detecting operation is performed. Because the threshold voltage detecting operation performed here is similar to the case of the structure of FIG. 12, description is omitted.
In the first half of the time period of T3 shown in FIG. 19, programming operation is performed. Because the programming operation performed here also is similar to the case of the structure of FIG. 12, description is omitted.
In the second half of the time period of T3 shown in FIG. 19, i.e., after the programming operation, correction operation of the mobility μ is performed, and the program voltage is corrected.
In the technique disclosed in JP-A No. 2003-271095 described in FIG. 12, when the programming operation finishes, the Scan signal is immediately made to be non-selection level and the light-emitting operation is started. However, here, the Scan signal is maintained at the selection level and the selection gate connecting switch 100 is held in the on state for a set time (=Tx) after completion of the programming operation.
During this time, the current Id, that corresponds to the programmed voltage Vod, flows to the driving transistor 104. The current Id is charged to the parasitic capacitance 108, and, as shown in FIG. 19, the source voltage Vs of the driving transistor 104 rises again. Given that the voltage that again rises is ΔV, ΔV can be expressed by the following formula.ΔV=Tx*Id/Cd 
Here, given that the time Tx and the capacity Cd of the parasitic capacitance 108 are common to all of the pixels, ΔV is a function of the current Id.
Further, as mentioned previously, the saturated region current formula of a TFT isId =μ*Cox*(W/L)*(Vgs−Vth)2,and the threshold voltage Vth is already corrected in time period T2. Therefore,Id=μ*Cox*(W/L)*Vod2.
Accordingly, ΔV will be a voltage corresponding to ρ*Cox*(W/L) of each driving transistor 104, and the voltage Vcs of the retention capacitor 102 is held at a voltage “Vth+Vod−ΔV” that is obtained by subtracting ΔV from the voltage Vgs between the gate and the source (as described previously, Vgs=Vth+Vod). Due thereto, the μ deviations of the driving transistors 104 of each of the pixels are cancelled. Namely, the greater the mobility μ, the larger the ΔV. The smaller the mobility μ, the smaller the ΔV. Therefore, the program voltage is corrected by this deviation.
In time period T4 shown in FIG. 19, light-emitting operation is performed. In the light-emitting time period T4, the Scan signal is set to the non-selection level, and the selection gate connecting switch 100 turns off. Further, while the voltages at both ends of the retention capacitor 102 are held as is, the parasitic capacitance 108 of the OLED 106 is charged with the current Id that flows to the driving transistor 104, and the source voltage Vs rises. The voltage Vgs between the gate and the source of the driving transistor 104 remains retention the program voltage. Accordingly, eventually, the source voltage Vs exceeds the light-emitting threshold voltage Vf0 of the OLED 106, and the OLED 106 emits light.
However, there are the following problems in the above-described conventional art.
In the techniques disclosed in above-described JP-A No. 2003-271095 and JP-A No. 2007-310311, in the resetting time period T1, the source voltage Vs of the driving transistor 104 must be reset (made to be 0 V in the above example) in the initial state. This is realized by natural discharging of OLED leak current in the circuit disclosed in exemplary embodiment 1 of JP-A No. 2003-271095, and is realized by controlling the power supply voltage with respect to the driving transistor 104 and discharging to the power supply line 118 via the driving transistor 104 in the circuit disclosed in JP-A No. 2007-310311.
However, in both, a certain amount of time is needed for the discharging, and incorporation into a panel of a large number of pixels is difficult due to the restrictions on the program time period.
Therefore, as described in FIG. 12, a transistor switch for OLED parasitic capacitance discharge, that is for actively making the source voltage Vs of the driving transistor 104 be the reset voltage (0 V in this case), i.e., the reset switch 110 as described above, is needed. However, separately providing such a reset switch 110 becomes a primary factor in increased costs due to decreased yield, and in decreased lifespan due to a decreased OLED aperture ratio.
Moreover, there is the problem of errors in threshold voltage detection, due to color pixel deviations between pixels of plural reference colors, of the parasitic capacitances of the diode elements. Here, the problem of color deviations will be described with reference to FIG. 12, FIG. 18 and FIG. 20 through FIG. 24 that illustrate structures of conventional art.
In the above-described technique disclosed in JP-A No. 2003-271095, in the operation of detecting the threshold voltage Vth, the voltage Vgs between the gate and the source when the current Id becomes sufficiently small and the rise in the source voltage Vs stops, is set as the threshold voltage Vth. However, in an actual TFT, voltage (Von) at which the current actually flows-out and the threshold voltage Vth of the saturation region current formula differ due to the current characteristics of the sub-threshold region (here, the sub-threshold region means a region that is less than or equal to Vth).
The overdrive voltage Vod, that is set in the programming operation in time period T3, is voltage that is computed from the saturation region current formula. The voltage for which determination is desired in the threshold voltage Vth detecting operation is the Vth in the current formula, and is not Von. However, the voltage that is actually detected in the threshold voltage Vth detecting operation in the technique of JP-A No. 2003-271095 is the voltage Von that is different from the threshold voltage Vth in the current formula.
This point will be explained with reference to FIG. 20 and FIG. 21.
FIG. 20 is an example of a graph showing Vgs-Id characteristics of TFTs. In this graph, Vgs is shown on the X-axis and Id is shown on the Y-axis. The Vgs-Id characteristic of a TFT whose sub-threshold region current is small is shown by the thick line, and the Vgs-Id characteristic of a TFT whose sub-threshold region current is large is shown by the thin line. Although the difference between the two is not remarkable in this graph, the difference becomes clear when the relationship between the square root of the current Id and Vgs is graphed. FIG. 21 is an example of a graph showing Vgs-√Id characteristics. In this graph, Vgs is shown on the X-axis and √Id is shown on the Y-axis. In the same way as in FIG. 20, the Vgs-√Id characteristic of a TFT whose sub-threshold region current is small is shown by the thick line, and the Vgs-√Id characteristic of a TFT whose sub-threshold region current is large is shown by the thin line. Moreover, the straight line showing the threshold voltage Vth in the saturated region current formula (the calculated straight line of the threshold voltage Vth) is shown by the dashed line.
As is clear from FIG. 21, the threshold voltage that is shown by the extrapolated X intercept of the computed straight line of the threshold voltage Vth here is Vth=1.46 V. This value is the value that is desired to be set in the programming operation. However, due to the current characteristics of the sub-threshold region, the current Id when Vgs=Vth is different. Namely, the voltage Von at which current actually flows-out is lower than the Vth that is determined by the computed straight line of the threshold voltage Vth, and the value thereof differs in accordance with the current characteristics of the sub-threshold region (refer to Von1, Von2 of FIG. 21).
This means that, in the threshold voltage Vth detection operation at the above-described conventional pixel circuit, in order to detect Vth and not Von, the charging of the retention capacitor 102 is needed to be stopped when a predetermined time period elapses, before the rise of the source voltage Vs is saturated.
The threshold voltage Vth detection time period is determined by the current characteristics of the sub-threshold region of the driving transistor 104 and the magnitude (capacity) of the parasitic capacitance 108.
Here, the relationship between the capacity of the parasitic capacitance 108 and the threshold voltage detection time period, of each current characteristic of the sub-threshold region, will be described with reference to FIG. 22 and FIG. 23.
FIG. 22 is a graph showing examples of the results of simulation of threshold voltage detection operation in cases in which the capacity Cd of the parasitic capacitance 108 is 2 pF and 4 pF, at a TFT whose sub-threshold region current is small.
FIG. 23 is a graph showing examples of the results of simulation of threshold voltage detection operation in cases in which the capacity Cd of the parasitic capacitance 108 is 2 pF and 4 pF, at a TFT whose sub-threshold region current is large.
In both graphs, the horizontal axis is the threshold voltage Vth detection time period t(s), and the vertical axis is the voltage Vgs between the gate and the source. The results of simulation in the cases in which the capacity Cd is 4 pF are shown by the thick lines, and the results of simulation in the cases in which the capacity Cd is 2 pF are shown by the thin lines. The dashed lines in the graphs show the threshold voltage of 1.46 V.
As is clear from FIG. 22, in the case of the TFT whose sub-threshold region current is small, the threshold voltage detection time period is around 50 μs in all cases. Even if the capacity Cd of the parasitic capacitance 108 varies, the threshold voltage detection time period does not change, and therefore, large errors do not arise in the detected value of the threshold voltage Vth.
On the other hand, as is clear from FIG. 23, in the case of the TFT whose sub-threshold region current is large, the threshold voltage detection time period is around 20 μs in the case in which the capacity Cd is 4 pF. However, in the case in which the capacity Cd is 2 pF, the threshold voltage detection time period varies greatly, and a large error will arise in the detected value of the threshold voltage Vth.
From the above, it can be understood that the threshold voltage Vth detection time period varies greatly in accordance with the magnitude of the parasitic capacitance 108 when a TFT whose sub-threshold region current is large is used as the driving transistor 104 in an organic EL display device.
The capacity of the parasitic capacitance 108 of the OLED 106 is usually around 150 to 300 pF/mm2. This value is determined mainly from the relative permittivity (dielectric constant) and the film thickness of the organic light-emitting material. The dielectric constant and the film thickness differ in accordance with the color (RGB) of the OLED 106, and therefore, the parasitic capacity differs at each color of the OLEDs 106.
Generally, in an active matrix system organic EL display device, the lines of each color in which pixels per color of RGB are lined-up in the column direction (the Data line direction) are structured so as to be disposed in order of, for example, RGBRGB . . . in the row direction (the Scan line direction). Because the respective pixel circuits on a same Scan line are controlled at the same timing, the detection time periods of the threshold voltage Vth are common for RGB. However, as described above, in the case of a driving transistor 104 whose sub-threshold region current is large, the threshold voltage Vth detection time period depends on the magnitude of the parasitic capacitance 108 of the OLED 106, and therefore, errors in detection of the threshold voltages Vth arise due to capacity deviations between each pixels of RGB (RGB deviations).
Also in the pixel circuit that performs μ correction that is disclosed in JP-A No. 2007-310311, ΔV =Tx*Id/Cd, and the RGB deviations of the parasitic capacitances 108 are a cause of errors.
As a method of addressing the above fact, as shown in FIG. 24, there is a method of setting, at each pixel, a correction capacitor 120 that makes the electrostatic capacity that is connected to the source of the driving transistor 104 to be the same among pixels of RGB. However, this leads to a decrease in the OLED lifespan due to a decrease in the aperture ratio, and to an increase in costs due to a decrease in yield.